There is no semiconductor design that exists in isolation. Every chip shipped by a fabless company sits on a foundation of licensed IP — processor cores, interface PHYs, memory controllers, standard cell libraries — that the team didn't write and may not fully understand. Gurpreet S. Bal has advised on semiconductor transactions where IP licensing structure was the most complex element of diligence. "Every chip design team is essentially building on top of licensed IP they didn't create, and the restrictions in those licenses travel with the design in ways the engineering team often doesn't know about," he says.
Bal's semiconductor practice spans M&A transactions, licensing disputes, and export control analysis for chip companies from early-stage to late-stage, including acquirers evaluating semiconductor assets.
Semiconductor IP comes in two primary forms: soft cores (delivered as synthesizable RTL that the licensee can modify and target to any process node) and hard cores (pre-characterized, layout-complete implementations optimized for a specific foundry and process). The distinction matters enormously for licensing terms. Hard core licenses are typically more restrictive — tied to a specific foundry relationship, often non-transferable, and sometimes subject to per-unit royalties that the original licensee must flow through to any transferee. Soft core licenses are more portable but may restrict modification, sublicensing, and redistribution. Arm's architecture licenses, for instance, allow licensees to implement custom microarchitectures, but those implementations remain subject to Arm's compliance requirements and the license terminates if certain conditions aren't met. In an M&A context, the question is always whether the license survives change of control — and for many semiconductor IP licenses, it does not without the licensor's written consent.
Electronic design automation tools — Synopsys, Cadence, Siemens EDA — are licensed per seat, per server, per feature module, and sometimes per design. License audits are a real and recurring event in the semiconductor industry. EDA vendors maintain server-side telemetry and reserve contractual audit rights that allow them to review usage logs going back multiple years. The consequence of a license shortfall — more seats used than licensed, features accessed outside the licensed scope, use of tools on servers not covered by the agreement — can be significant: back payments, compliance penalties, and in some cases license termination. The audit risk intensifies in high-growth environments where design teams expand rapidly and tool usage outruns procurement. Companies preparing for an IPO or M&A transaction should conduct an internal EDA license compliance review before those processes begin, not after a buyer or auditor raises the question.
Process design kits are foundry-proprietary and licensed under terms that restrict how the design data can be used, stored, shared, and transferred. TSMC, Samsung, GlobalFoundries, and Intel Foundry each have their own PDK license agreements, and those agreements typically prohibit using the PDK to design chips for any other foundry. This isn't just a competitive restriction — it creates genuine IP exposure if design data developed under one foundry's PDK is transferred to another context. In M&A transactions involving semiconductor IP, the target's PDK licenses must be reviewed to determine whether the acquired design data can be used in the acquirer's existing foundry relationships, or whether new PDK licenses are required. Foundry relationships are also frequently non-assignable, meaning a change of control may require renegotiating the manufacturing relationship from scratch.
Semiconductor technology is a priority category under both the International Traffic in Arms Regulations (ITAR) and the Export Administration Regulations (EAR). Technical data controlled under these regimes — which can include design files, schematics, test results, and fabrication data for controlled technology nodes — cannot be transferred to foreign nationals, foreign companies, or foreign destinations without an appropriate license or license exception. The "deemed export" rule is particularly consequential: sharing controlled technical data with a non-U.S. person in the United States is treated as an export to that person's country of nationality. For semiconductor companies with international engineering teams, this creates compliance obligations around who can access what design data. In transactions involving foreign acquirers or investors, CFIUS review of semiconductor IP transfers has become essentially mandatory at advanced process nodes, and export control classification of the IP portfolio is a threshold diligence task.
Standard-essential patents (SEPs) covering wireless connectivity standards — 5G, Wi-Fi, Bluetooth — must be licensed on fair, reasonable, and non-discriminatory (FRAND) terms by commitments made to standards development organizations like ETSI, IEEE, and ITU. For companies shipping chips that implement these standards, this means navigating licensing negotiations with large SEP holders, some of whom are also direct competitors. FRAND rates are negotiated bilaterally and, when disputes arise, litigated — often in multiple jurisdictions simultaneously. Patent pools like Avanci attempt to simplify the process by aggregating licenses from multiple SEP holders into a single per-unit royalty, but pool participation is voluntary and some major holders remain outside these structures. Chips targeted at connected devices carry a royalty stack that needs to be modeled before production commitments are made.
Gurpreet S. Bal is a corporate partner with 16 years advising on private equity, merger transactions, and public offerings for companies and investors at three of the world's top law firms. He has represented clients in hundreds of transactions with aggregate deal value exceeding $60 billion across AI, semiconductors, fintech, and emerging technology. For more information and to get in touch, visit gurpreetbal.com.